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d a t a sh eet product speci?cation file under integrated circuits, ic02 1996 jul 30 integrated circuits TDA8706A 6-bit analog-to-digital converter with multiplexer and clamp
1996 jul 30 2 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A features 6-bit resolution binary 3-state cmos outputs cmos compatible digital inputs 3 multiplexed video inputs r, g and b clamps on code 0 single 6-bit adc operation allowed up to 40 msps external control of clamping level internal reference voltage (external reference allowed) power dissipation only 36 mw (typical) operating temperature of - 40 to +85 c operating between 2.7 and 5.5 v. applications general purpose video applications r, g and b signals automotive (car navigation) lcd systems frame grabber. general description the TDA8706A is a 6-bit analog-to-digital converter (adc) with 3 analog multiplexed inputs. each input has an analog clamp on code 0 for rgb video processing. clamping level can also be adjusted externally up to code 20. it can also be used as a single 6-bit adc. quick reference data ordering information symbol parameter conditions min. typ. max. unit v dda analog supply voltage 2.7 3.0 5.5 v v ddd digital supply voltage 2.7 3.0 5.5 v v ddo output stages supply voltage 2.7 3.0 5.5 v i dda analog supply current - 710ma i ddd digital supply current - 46ma i ddo output stages supply current f clk = 40 mhz; ramp input - 1 1.5 ma inl integral non-linearity f clk = 40 mhz; ramp input; t amb =25 c - 0.25 0.6 lsb dnl differential non-linearity f clk = 40 mhz; ramp input; t amb =25 c - 0.20 0.5 lsb f clk(max) maximum clock frequency 40 -- mhz p tot total power dissipation f clk = 40 mhz; ramp input 3 v supplies - 36 - mw 5.5 v supplies -- 96 mw type number package name description version TDA8706Am ssop24 plastic shrink small outline package; 24 leads; body width 5.3 mm sot340-1
1996 jul 30 3 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A block diagram fig.1 block diagram. handbook, full pagewidth multiplexer 6-bit adc cmos outputs regulator 4 8 9 10 22 sr sg sb 5 21 23 123 6 7 14 select inputs 24 15 13 12 11 d0 16 d1 17 d2 18 d3 19 d4 20 d5 digital voltage outputs mgd133 TDA8706A clp red green blue v ssd v ddo v dda v ddd v dda v rb v ssa v sso clk v clpb v clpg v clpr clamp
1996 jul 30 4 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A pinning symbol pin description sr 1 select input red sg 2 select input green sb 3 select input blue clp 4 clamping pulse input (positive pulse) v dda 5 analog supply voltage v rb 6 reference voltage bottom input v ssa 7 analog ground red 8 red input green 9 green input blue 10 blue input v clpr 11 red clamping voltage level input v clpb 12 blue clamping voltage level input v clpg 13 green clamping voltage level input v sso 14 digital output ground d0 15 digital voltage output; bit 0 (lsb) d1 16 digital voltage output; bit 1 d2 17 digital voltage output; bit 2 d3 18 digital voltage output; bit 3 d4 19 digital voltage output; bit 4 d5 20 digital voltage output; bit 5 v ddo 21 supply voltage for output stage v ssd 22 digital ground v ddd 23 digital supply voltage clk 24 clock input fig.2 pin configuration. handbook, halfpage TDA8706A mgd132 1 2 3 4 5 6 7 8 9 10 11 12 24 clk v ddd v ssd v ddo d5 d4 d3 d2 d1 d0 v sso v clpb sr sg sb clp v dda v rb v ssa red green blue v clpr v clpg 23 22 21 20 19 18 17 16 15 14 13
1996 jul 30 5 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A limiting values in accordance with the absolute maximum rating system (iec 134). handling inputs and outputs are protected against electrostatic discharges in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. thermal characteristics symbol parameter min. max. unit v dda analog supply voltage - 0.3 +7.0 v v ddd digital supply voltage - 0.3 +7.0 v d v dd supply voltage difference v dda - v ddd - 1.0 +1.0 v v dda - v ddo - 1.0 +1.0 v v ddd - v ddo - 1.0 +1.0 v v i input voltage - 0.3 +7.0 v i o output current - 10 ma t stg storage temperature - 55 +150 c t amb operating ambient temperature - 40 +85 c t j junction temperature - +150 c symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 119 k/w
1996 jul 30 6 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A characteristics v dda =v 5 to v 7 = 2.7 to 5.5 v; v ddd =v 23 to v 22 = 2.7 to 5.5 v; v ddo =v 21 to v 14 = 2.7 to 5.5 v; v ssa ,v ssd and v sso shorted together; v i(p-p) = 0.7 v; t amb = - 40 to +85 c; typical values measured at v dda =v ddd =v ddo = 3 v and t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v dda analog supply voltage 2.7 3.0 5.5 v v ddd digital supply voltage 2.7 3.0 5.5 v v ddo output stages supply voltage 2.7 3.0 5.5 v d v dd supply voltage difference v dda - v ddd - 0.3 - +0.3 v v dda - v ddo - 0.3 - +0.3 v v ddd - v ddo - 0.3 - +0.3 v i dda analog supply current - 710ma i ddd digital supply current - 46ma i ddo output stages supply current f clk = 40 mhz; ramp input - 1 1.5 ma inputs c lock input clk ( referenced to v ssd ); note 1 v il low level input voltage 0 - v ddd 0.3 v v ddd < 3.3 v 0 - v ddd 0.2 v v ih high level input voltage v ddd 0.7 - v ddd v v ddd < 3.3 v v ddd 0.8 - v ddd v i il low level input current v clk =v ddd 0.2 - 10 +1 m a i ih high level input current v clk =v ddd 0.8 - 210 m a z i input impedance f clk = 40 mhz - 4 - k w c i input capacitance f clk = 40 mhz - 3 - pf i nputs sr, sg, sb, clp ( referenced to v ssd ) v il low level input voltage 0 - v ddd 0.3 v v ddd < 3.3 v 0 - v ddd 0.2 v v ih high level input voltage v ddd 0.7 - v ddd v v ddd < 3.3 v v ddd 0.8 - v ddd v i il low level input current v il =v ddd 0.2 - 1 --m a i ih high level input current v ih =v ddd 0.8 -- +1 m a i nputs v clpr ,v clpg and v clpb ( referenced to v ssa ); see tables 1 and 2 v clp input voltage for clamping v code - 9 - v code 20 v i clp input current -- 30 m a
1996 jul 30 7 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A a nalog inputs red, green and blue; see table 1 v i(p-p) input voltage amplitude (peak-to-peak value) v dda =v ddd =3v; t amb =25 c 0.665 0.70 0.735 v v dda =v ddd =5v; t amb =25 c 0.625 0.66 0.695 v i i input current -- 10 m a c clamp clamp coupling capacitance 1 10 100 nf reference voltages for the resistor ladder; see table 1 v rb reference voltage bottom v dda =3v - v dda - 1.19 - v v dda =5v - v dda - 1.13 - v d t vrb temperature variation on v rb t amb = 0 to 50 c - 0.7 - mv/ c outputs d igital outputs d5 to d0 ( referenced to v ssd ) v ol low level output voltage i o = 1 ma 0 - 0.5 v v oh high level output voltage i o = - 1ma v ddo - 0.5 - v ddo v switching characteristics c lock input clk; see fig.3; note 1 f clk(max) maximum clock frequency 40 -- mhz f mux(max) maximum multiplexer frequency 20 -- mhz t cph clock pulse width high 8 -- ns t cpl clock pulse width low 8 -- ns t r clock rise time 10% to 90%; f clk 25 mhz; low=v ssd , high = v ddd -- 10 ns t f clock fall time 90% to 10%; f clk 25 mhz; low=v ssd , high = v ddd -- 10 ns analog signal processing l inearity inl integral non-linearity f clk = 40 mhz; ramp input; t amb =25 c - 0.25 0.6 lsb dnl differential non-linearity f clk = 40 mhz; ramp input; t amb =25 c - 0.20 0.5 lsb e ffective bits ; note 2 eb effective bits f clk = 40 mhz; f i = 4.43 mhz - 5.8 - bits symbol parameter conditions min. typ. max. unit
1996 jul 30 8 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A notes 1. in addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns. 2. effective bits are obtained via a fast fourier transform (fft) treatment taking 8k acquisition points per equivalent fundamental period. the calculation takes into account all harmonics and noise up to half of the clock frequency (nyquist frequency). conversion to signal-to-noise ratio: s/n = eb 6.02 + 1.76 db. 3. output data acquisition: the output data is available after the maximum delay time of t d . timing (f clk = 40 mhz; c l = 20 pf); t amb =25 c; see fig.3 o utput data ; note 3 t ds sampling delay time -- 7ns t h output hold time 5 -- ns t d output delay time v ddo = 4.75 v - 12 15 ns v ddo = 3.15 v - 17 20 ns v ddo = 2.70 v - 18 21 ns s elect input signals sr, sg, sb and clp t su set-up time sr, sg and sb with no overlap; see fig.3 10 -- ns with overlap see fig.4 ns t r rise time sr, sg and sb 10% to 90% 4 6 - ns t f fall time sr, sg and sb 90% to 10% 4 6 - ns t over r, g and b (active) overlap time with respect to select signals sr, sg and sb see fig.4 0 -- ns t clpp clamp pulse time c clp =10nf - 3 -m s t mh multiplexer hold time sr, sg and sb 9 -- ns symbol parameter conditions min. typ. max. unit
1996 jul 30 9 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A table 1 output coding and input voltage (typical values) table 2 clamping input level (v clpr , v clpg and v clpb ) note 1. use capacitor 3 10 pf to v ssa . table 3 clamp and inputs red, green and blue; v dda =v ddd =v ddo =3v note 1. where x = dont care. table 4 clamping characteristic related to tv signals step v i(p-p) (v) binary output bits v dda =v ddd =3v v dda =v ddd = 5 v d5 d4 d3 d2 d1 d0 under?ow < v dda - 1.1 < v dda - 1.06 0 0 0 0 0 0 0v dda - 1.1 v dda - 1.06 0 0 0 0 0 0 1 . . 000001 . . . ...... . . . ...... 62 . . 111110 63 v dda - 0.4 v dda - 0.4 111111 over?ow > v dda - 0.4 > v dda - 0.4111111 v clpr , v clpg and v clpb clamping level open-circuit (1) code 0 v code - 9 to v code 20 code - 9 to code 20 sr or sg or sb clamp v clpr , v clpg or v clpb v i red or green or blue digital outputs 0 1 open v dda - 1.1 v x (1) v clp v clp 1 open v dda - 1.1 v 0 v clp v clp code (v clp ) parameter min. typ. max. unit clamping time per line (signal active) 2.2 3.0 -m s input signals clamped to correct level - 3 10 lines
1996 jul 30 10 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A fig.3 ac characteristics select signals, clamp and output data. handbook, full pagewidth mbe859 t cph t su t mh t d t h t clpp t cpl clk sr sg sb clamp output data green blue red green
1996 jul 30 11 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A fig.4 anti-overlap system for analog multiplexer. handbook, full pagewidth mbe860 sr clk sg sb red active green active blue active t over t su t over t over fig.5 ac characteristics select signals; clamp and data. handbook, full pagewidth 1 0 clamp input red, green, blue (sr, sg, sb inputs) digital outputs = 000000 mbe861
1996 jul 30 12 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A internal pin configurations fig.6 cmos data outputs. handbook, halfpage mgd134 v ddo v sso d5 to d0 fig.7 v rb . handbook, halfpage r lad mbe967 v rb v dda v ssa regulator fig.8 clk input. handbook, halfpage v ddd v ssd clk mlc860 1 / 2 v ddd
1996 jul 30 13 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A application information handbook, full pagewidth TDA8706A mbe969 1 2 3 4 5 6 7 8 9 10 11 12 24 clk v ddd v ssd v ddo d5 d4 d3 d2 d1 d0 v sso v clpb (2) sr sg sb clp v dda v rb (1) v ssa red green blue v clpr (2) v clpg (2) 23 22 21 20 19 18 17 16 15 14 13 v ssa 100 nf v ssa 100 nf v ssa 100 nf v ssa 100 nf the analog and digital supplies should be separated and decoupled. v rb must not be connected to v clpr , v clpb or v clpg pins. for applications where the black level is clamped to code 0, v clpr , v clpb and v clpg must be left open-circuit with their respective decoupling capacitors. in that event, they may also be connected together in order to use only one single decoupling capacitor. (1) v rb is decoupled to v ssa . eventually an external regulator can be connected to v rb . (2) v clpr , v clpb and v clpg are decoupled to v ssa . eventually external voltages can be forced on v clpr , v clpb and v clpg . fig.9 application diagram.
1996 jul 30 14 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A package outline unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 0.8 0.4 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.20 mm maximum per side are not included. 1.03 0.63 sot340-1 mo-150ag 93-09-08 95-02-04 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 112 24 13 0.25 y pin 1 index 0 2.5 5 mm scale ssop24: plastic shrink small outline package; 24 leads; body width 5.3 mm sot340-1 a max. 2.0
1996 jul 30 15 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all so and ssop packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering so wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. ssop wave soldering is not recommended for ssop packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. even with these conditions, only consider wave soldering ssop packages that have a body width of 4.4 mm, that is ssop16 (sot369-1) or ssop20 (sot266-1) . m ethod (so and ssop) during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 jul 30 16 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1996 jul 30 17 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A notes
1996 jul 30 18 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A notes
1996 jul 30 19 philips semiconductors product speci?cation 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A notes
internet: http://www.semiconductors.philips.com (1) TDA8706A_1 july 18, 1996 12:44 pm philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca51 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 926 5361, fax. +7 095 564 8323 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - 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